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STATUS: Rev.B Verified. Releasing rev.C. Some aesthetic changes made |
Figure 1. Schematic diagram B022 DCD
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Dsx/Drx are data inputs set/reset
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Csx/Crx are are clock inputs
The FFs are from BasFF (B010).
Dsx/Drx data is clocked in on the falling edge of Csx/Crx. Most of the time Csx/Crx signals are tied together. Nodes Sxa/Rxa are direct set/reset signals.
