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Tip STATUS: Development

This board make a 1.3824Mc or 691.2Kc four phase clock out of 1.8432Mc. The board must be combined with B020 to get a JK-FF function out of T1e/T1f & T1g/T1h. If buffer stage T1c/T1d is reconfigured to a JK-FF function then we get the 691.2Kc (1.45µs), which is close to the PDP-8 cycle time of 1.5µs. Extra logic can be added with the B010 board to get CPU wait stages, halt, etc. functions.

Figure 1. Schematic diagram B110 Four phase clock