MOV-1
»Home
»mov1
»isa
»progs
»vhdl
»refcard

A 16 bit Transport Triggered Architecture move processor

Table 1. Abbreviaitons

TTA

Transport Triggered Architecture

ISA

Instruction Set Architecture

ISR

Interupt Service Routine

FC

TTA Functional Unit

CU

TTA Control Unit (is a special FC)

CG

Constant Generator

HWA

Hardware address

HWD

Hardware data

PC

Program Counter

PCC

Program Counter Copy

ALU

Artitmetic Logic Unit

MU

Memory Unit

MA

Memory Address

MD

Memory Data

Q

Squash

L

Literal

CC

Move control bits

NOP

No OPeration

src

Source

des

Destination

Opr

Operand

Mne

Mnemonic

MOV-1 basics

MOV-1 uses the Von Neumann Architecture which has one memory for program data and variable data. The only intruction that MOV-1 has is a Guarded MOVE instruction. It moves data form a source to a destination address limited to 64 locations (six bit). The guard bits (Q bit) can select a conditional move. When a previous move was TRUE and the current move is a conditional move then the current move will be skipped. Because source and destination addresses are six bit, octal numbers are used for the addresses. The guard bits CC can select a operated move. While move from source to destination location a simple data modification can be done on source location.

Within the TTA address space are functional units (FU). A ALU is a FU. A special FU is the control unit (CU). This unit contols program flow. A jump is simply a write to the program counter (PC) which is located in the CU.

MOV-1 uses two forms of move opcodes. When L bit is cleared a move source to destination is performed. When L bit is set the source address plus move control bits CC are used as 8 bit literal value write to destination address.

FEDCBA9876543210
QLCCssssssdddddd   Opcode form 1: Move source to destination
QLlllllllldddddd   Opcode form 2: Move literal to destination.

QLCC               Guard bits. If L=1 then CC is in use for literal bits
Q                  Squash bit. Q=0: unconditional move. Q=1: conditional move
 L                 Literal
  CC               L=0 Move control
  llllllll         L=1 CC + Source address bits are used as literal byte
    ssssss         L=0 Source address
          dddddd   Destination address

MOV-1 can handle magnetic core memory. When using magnetic core memory a Write-back after a read is always performed because of the destructive read behaviour of core memory. Write means a write to destination address. Write-back means restore destroyed source data. MOV-1 uses a six phase clock which is in practice a six state state-machine. The CC bits select which state-machine sequence to be used.

Normal processor sequence
  1. Fetch opcode from memory

  2. Write-back fetched opcode

  3. Read source data from memory or a functional unit register

  4. Modify readed data

  5. Write data to distination

  6. Write back readed source memory data

Move control bits alter state 4 & 5 sequence
CC
00   MOV  : Read, NOP,           Write,  Write-back
01   RM1WB: Read, Modify type 1, Write,  Write-back
10   RM2WB: Read, Modify type 2, Write,  Write-back
11   RWMB : Read, Write,         Modify, Write-back

TTA address range 00-37o (0-31d) gives directly access to data memory locations 00-37o. This piece of fast access low memory is called the Register File (RF).

TTA address range 40-47o is Block Access Memory (BAM) pointed by register MA (Memory Address). The lowest three bits of the memory location are from TTA’s source/destination address 40-47o (0-7). The upper part is from MA:

Location = MA(15..3) & SRC/DES(2..0)

TTA address range 50-77o is in use by Functional Units (FC):

  • 50-57o MU Memory Unit

  • 60-67o ALU Arithmetic Logic Unit

  • 70-77o CU Control Unit

For more detail on MU, ALU and CU:

Memory layout

Interrupts are automatic disabled when running a service or interrupt routine. interrupt enable is bounded to the PC address and anded with the interrupts enable bit. When returning from an interrupt the interrupts are enabled again.

Memory is splitted in a ROM part which is in use by system routines and a RAM part which is in use for r/w data and user programs.

Normaly an interrupt routine will use the auxiliary register file. Using auxiliary registers avoids pushing and poping register on a software stack when servicing an interrupt.

Exchange auxiliary register file
        lit     1,MU+MSC        ; Use auxiliary register file
        lit     0,MU+MSC        ; Use default register file
Table 2. Memory Map
Octal Hex Size Type Int Desciption

000000..003777

0000..07FF

2k

ROM

No

Service (SRVC)

004000..077777

0800..0FFF

2k

ROM

No

Interrupt Service Routines System (ISRS)

010000..033777

1000..37FF

10k

ROM

Yes

System routines (SYS)

034000..037777

3800..3FFF

2k

IO

Yes

PRT 8 bit BAM: Memory mapped IO

040000..040037

4000..401F

32

RAM

No

Register file

040040..040077

4020..403F

32

RAM

No

Auxiliary register file

040100..043777

4040..47FF

2k

RAM

No

MAS 8 bit BAM: SRVC, ISRS and SYS RAM

044000..047777

4800..4FFF

2k

RAM

No

Interrupt Service Routine User (ISRU)

050000..053777

5000..57FF

2k

RAM

Yes

MAU 8 bit BAM: Fast access user RAM

054000..077777

6800..7FFF

10k

RAM

Yes

SYS RAM

100000..177777

8000..FFFF

32k

RAM

Yes

MMU banking

Interrupts & Service routines

MOV-1 has two interrupt modes.

Interrupt mode 0

This mode uses daisy-chain interrupt priority. When an interrupt occurs the core gives a interrupt acknowledge. The interrupt device puts an opcode on the data bus. Mostly this will be a JPH instruction. A copy of the current PC is made in the memory buffer MB.

Setup interrupt mode 0
        lit     0,MU+MC         ; Reset memory control
        lit     #20,CU+CSC      ; Enable interrupts and select interrupt mode 0
Interrupt service routine system
ORG 8#104000
ISRS:
        mov     MU+MB,8#37      ; Catch return address
        lit     1,MU+MSC        ; Use auxiliary registers

        .................       ; Interrupt routine

        lit     0,MU+MC         ; Use default registers
        mov     8#37,CU+PC      ; Return from interrupt

Interrupt mode 1

In this mode the CU generates an opcode JPH to fixed address 8#104000.

Setup interrupt mode 1
        lit     0,MU+MC         ; Reset memory control
        lit     #30,CU+CSC      ; Enable interrupts and select interrupt mode 1