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FEDCBA9876543210
QLCCssssssdddddd   Opcode form 1: Move source to destination
QLlllllllldddddd   Opcode form 2: Move literal to destination.

QLCC               Guard bits. If L=1 then CC is in use for literal bits
Q                  Squash bit. Q=0: unconditional move. Q=1: conditional move
 L                 Literal
  CC               L=0 Move control
  llllllll         L=1 CC + Source address bits are used as literal byte
    ssssss         L=0 Source address
          dddddd   Destination address

Move control bits
CC
00   MOV  : Read, NOP,           Write,  Write-back
01   RM1WB: Read, Modify type 1, Write,  Write-back
10   RM2WB: Read, Modify type 2, Write,  Write-back
11   RWMB : Read, Write,         Modify, Write-back
Table 1. Native opcodes
Mne Opr Description

lit

L,D

[01 llllllll dddddd] Load literal

mov

S,D

[0000 ssssss dddddd] Move

rm1wb

S,D

[0010 ssssss dddddd] Operated move type 1

rm2wb

S,D

[0011 ssssss dddddd] Operated move type 2

rwmb

S,D

[0001 ssssss dddddd] Operated move type 0

clit

L,D

[11 llllllll dddddd] Conditional load literal

cmov

S,D

[1000 ssssss dddddd] Conditional move

crm1wb

S,D

[1010 ssssss dddddd] Conditional operated move type 1

crm2wb

S,D

[1011 ssssss dddddd] Conditional operated move type 2

crwmb

S,D

[1001 ssssss dddddd] Conditional operated move type 0

Table 2. Single word macro opcodes (Combination of native opcodes and MU/ALU/CU memory/registers)
Mne Opr Description

jph

L

Jump 8 bit literal to segment 256 word aligned

jpl

L

Jump 8 bit literal within 256 word segment

srvc

L

Jump 8 bit literal to service routine <2k 8 word aligned

jpr

R

Jump far 16 bit register

cjph

L

Conditional jump 8 bit literal to segment 256 word aligned

cjpl

L

Conditional jump 8 bit literal within 256 word segment

csrvc

L

Conditional jump 8 bit literal to <2k 8 word aligned

cjpr

R

Conditional jump far 16 bit register

mvi

S,D

Memory MoVe then Increment source memory

imv

S,D

Memory Increment and then MoVe

dmv

S,D

Memory Decrement and then MoVe

inc

R

Memory increment

dec

R

Memory decrement

cmvi

S,D

Conditional memory MoVe then Increment source memory

cimv

S,D

Conditional memory Increment and then MoVe

cdmv

S,D

Conditional memory Decrement and then MoVe

cinc

S

Conditional memory increment

cdec

S

Conditional memory decrement

clear

S

Clear register

testV

Test overflow flag

halt

Halt processor. A reset can startup the processor again

sleep

Sleep processor. Interrupt or start switch wakeup the CU

bit00

D

Copy & test bit R00,Rxx & test bit R00,Rxx 0

bit01

D

Copy & test bit R00,Rxx & test bit R00,Rxx 1

bit02

D

Copy & test bit R00,Rxx & test bit R00,Rxx 2

bit03

D

Copy & test bit R00,Rxx & test bit R00,Rxx 3

bit04

D

Copy & test bit R00,Rxx & test bit R00,Rxx 4

bit05

D

Copy & test bit R00,Rxx & test bit R00,Rxx 5

bit06

D

Copy & test bit R00,Rxx & test bit R00,Rxx 6

bit07

D

Copy & test bit R00,Rxx & test bit R00,Rxx 7

bit08

D

Copy & test bit R00,Rxx & test bit R00,Rxx 8

bit09

D

Copy & test bit R00,Rxx & test bit R00,Rxx 9

bit10

D

Copy & test bit R00,Rxx & test bit R00,Rxx 10

bit11

D

Copy & test bit R00,Rxx & test bit R00,Rxx 11

bit12

D

Copy & test bit R00,Rxx & test bit R00,Rxx 12

bit13

D

Copy & test bit R00,Rxx & test bit R00,Rxx 13

bit14

D

Copy & test bit R00,Rxx & test bit R00,Rxx 14

bit15

D

Copy & test bit R00,Rxx & test bit R00,Rxx 15

Table 3. Multi word macro opcodes (Combination of native opcodes and MU/ALU/CU memory/registers)
Mne Opr Description

llit

LL,D

(2W) Load 16 bit literal

jmp

LL

(2W) Jump far 16 bit literal

swap

S,D

(2W) Swap low/high byte

pack

S1,S2,D

(3W) Pack two low bytes to 16 bit word

shr8

S,D

(2W) Shift right 8 bits

shl8

S,D

(2W) Shift left 8 bits

TTA map

Source and destination addresses are 6 bit width and ussing octal numbers is more convenient in this case. The TTA address are split up in 3 bits parts. First part addresses a Functional Unit (FU). Second part address a register within a FU.

Table 4. FU address map
Addr Mne Description

0-3

RF

Register File 00-37

4

MDB

Memory Data Block access

5

MU

Memory Unit

6

ALU

Arithmetic Logic Unit

7

CU

Control Unit

(0-3) Memory register file (MRF)

The register file is mapped into memory locations 00..37 o. Simple count up/down operations can be performed on the source registers with help of operated move RMWW/RWM1W/RWM2W.

(4) Block access memory (BAM)

A block of eight memory data words can be accessed with map 40..47o plus MA. The three low bits of 40..47o (0..7) is padded with MA upper bits (15..3).

Location = MA(15..3) & SRC/DES(2..0)

Simple count up/down operations can be performed on the MDB with help of operated move RM1WB/RM2WB/RWMB.

A MDB to MDB move with same source and destination address will clear the location.

(5) Memory Unit (MU)

Table 5. MU map
Addr Mne R/W Description

50

MU

-

Slot ID Memory Unit

0

MAS

w

8 bit MA 0 0000 aaaa aaaa 000

1

MAU

w

8 bit MA 0 0001 aaaa aaaa 000

2

PRT

w

8 bit MA 1 1111 aaaa aaaa 000

3

MSC

w

MU status & control

4

SEG1

w

Segment registers 0 and 1

5

SEG2

w

Segment registers 2 and 3

6

MA

r/w

16 bit Memory Address

7

MD

r/w

Memory Data

0

MBSHL

r

Memory Buffer Shift Left

1

MBSAL

r

Memory Buffer Shift Arithmetic Left

1

MB

r

Memory Buffer

2

MBROL

r

Memory Buffer Rotate Left

3

MBSHR

r

Memory Buffer Shift Right

4

MBSAR

r

Memory Buffer Shift Arithmetic Right

5

MBROR

r

Memory Buffer Rotate Right

A single memory data word read/write can be done with MA/MD
   llit  (var1>>>1),MU+MA     ; MA points to var1 (smal32 uses byte align!)
   mov   MU+MD,8#00           ; Move data point by MA to register 00
MS/MC bits
Write
-------- ------0-          Do not test zero flag
-------- ------10   tZ     Zero
-------- ------11   tNZ    Not Zero
-------- ----0---          Do not test sign flag
-------- ----10--   tS     Sign
-------- ----11--   tNS    Not Sign
-------- --0-----          Do not test carry flag
-------- --10----   tC     Carry
-------- --11----   tNC    Not Carry
-------- 0-------          Do not touch carry
-------- 10------   CRCA   Clear carry
-------- 11------   STCA   Set carry

Read
-----CSZ 1Cbbbbbb          With the 1C read tick a copy of MS can be made and a
                           write back to MC will correctly restore the carry flag
Table 6. Alias when des=NOP
Move Mne

imv R,ALU+ZERO

inc R

dmv R,ALU+ZERO

dec R

Code fragment count loop
   llit  3,8#00   ; Loop 3 times
   clear 8#02

loop:
   inc   8#02
   dec   8#00
   cjpl  loop
   halt           ; 8#00 = 0  8#02 = 3

(6) Arithmetic Logic Unit (ALU)

Table 7. ALU register map
Addr Mne R/W Description

60

ALU

-

Slot ID ALU

0

ACCU

r

Accumulator (ADD/SUB)

1

OPAN

r

NOT A

2

AND

r

A and B

3

OR

r

A or B

4

XOR

r

A xor B

5

OV

r

Test overflow flag

6

ZERO

r/w

Read ZERO (clear) / Write NUL (dump)

7

ASC

r/w

[----VCSZ sCtCtStZ] ALU Status and Control (ASCH read only)

0

SHL

r

(rmww) Shift Left

1

RCL

r

(rmww) Rotate trough Carry Left

2

SAL

r

(rmww) Shift Arithmetic Left

3

SBL

r

(rmww) Shift 4 bit Barrel Left

4

SHR

r

(rmww) Shift Right

5

RCR

r

(rmww) Rotate trough Carry Rigth

6

SAR

r

(rmww) Shift Arithmetic Right

7

SBR

r

(rmww) Shift 4 bit Barrel Right

ACCU (accumulator) does a carry add/sub with OPA=R27 & OPB=MA. The carry flag needs to be cleared when add or set when sub prior reading ACCU. Setting the carry flag will automatic selects substration (use of NOT OPB).

A bit test on OPA(7..0) can be done when using rwm1w and reading ALU(0..7). A bit test on OPA(15..8) can be done when using rwm2w and reading ALU(0..7). The bit is moved to LSB of destination and a register zero test is done.

Test bit 3 of R05
        mov     8#05,ALU+OPA
        rwm1w   ALU+3,ALU+NUL   ; Dump bit
        cjpl    BitIsNotZero    ; Skip jump if zero bit is set

A read of OV will move overflow flag to LSB of destination and a register zero test is done.

Test overflow flag
        mov     ALU+OV,ALU+NUL  ; Dump flag
        cjpl    NoOverflow      ; Skip jump if overflow bit is set
AS/AC bits
Write
-------- ------0-          Do not test zero flag
-------- ------10   tZ     Zero
-------- ------11   tNZ    Not Zero
-------- ----0---          Do not test sign flag
-------- ----10--   tS     Sign
-------- ----11--   tNS    Not Sign
-------- --0-----          Do not test carry flag
-------- --10----   tC     Carry
-------- --11----   tNC    Not Carry
-------- 0-------          Do not touch carry
-------- 10------   CRCA   Clear carry
-------- 11------   STCA   Set carry

Read
----VCSZ 1bbbbbbb          MSB of ASCL is always set to one and thus
                           a write back will restore the carry flag
Code examples
Example1:
; Add: R02 = R00 + R01
        mov     8#00,8#27       ; Load OPA
        mov     8#01,MU+MA      ; Load OPB
        lit     CRCY,ALU+MSC    ; Clear carry before add
        mov     ALU+ACCU,8#02   ; Store result
        mov     ASC,8#03        ; Store flags. Flags are valid after ACCU read
        ret

Example2:
; Substract: R02 = R00 - R01
        mov     8#00,8#27       ; Load OPA
        mov     8#01,MU+MA      ; Load OPB
        lit     STCY,ALU+MSC    ; Set carry before add
        mov     ALU+ACCU,8#02   ; Store result
        mov     ASC,8#03        ; Store flags. Flags are valid after ACCU read
        ret

Example3:
; Add two 32b unsigned numbers
; Sum = 123000 + 456000 = 579000
; Sum = 1 E078 + 6 F540 = 8 D5B8

OPA     = 8#27
OPB     = MU+MA

        llit    #E078,OPA
        llit    #F540,OPB
        lit     CRCY,ASC        ; Clear carry
        mov     ALU+ACCU,8#00   ; Low word
        llit    1,OPA
        llit    6,OPB
        mov     ALU+ACCU,8#01   ; High word
        ret

(7) Control Unit (CU)

The CU is infact a special FC.

Table 8. CU address map
Addr Mne R/W Description

70

CU

-

Slot ID Control Unit

0

CSC

r/w

CU status & control

2

CG

r/w

Lit 16 generator & HW port address

3

SWCG

r

CG read back with low/high byte swapped

3

CGH

w

Load CG high byte

4

L8CG

r

CG read back 8b shifted left

4

JPL

w

PC Jump whitin 256 word segment (8 bit)

5

R8CG

r

CG read back 8b shifted right

5

JPH

w

PC Jump to 256 word aligned segment (8 bit)

6

CGL

r

Read CG 8 bit high byte is cleared

6

SRVC

w

PC Service routine low mem <2k 8 word aligned (8 bit)

7

PC

r

PC next opcode

7

JMP

w

PC Jump (16 bit)

Jump

A jump is simply a write to the PC. A single literal write is 8 bits. To get a better code density several useful 8 bits jumps are available

Eight bit jumps
   jpl   loop           ; PCC <- PC, PC <- ---PC---AAAAAAAA
   jph   ChatProgram    ; PCC <- PC, PC <- AAAAAAAA00000000
   srvc  GetKey         ; PCC <- PC, PC <- 00000AAAAAAAA000
Sixteen bit jump
; PCC <- PC, PC <- AAAAAAAAAAAAAAAA
   jpr   8#00           ; Jump address is in register 8#00
   llit  CalcSqrt       ; Two literal writes

(0) Status/Control

Control bits
H-------   Halt
-S------   Sleep
--I-----   Interupt enable
---P----   Programing RAM

(2-3) Constant Generator usage

When doing a literal move to destination then CG low byte is packed high with the literal value low e.i.: CG low is mapped into the high byte of the destination

A move literal to CG will write the low byte and preserve the high byte. A move REG to CG will write low+high byte of CG.

Code fragments
; Macro 'llit LL,D'
; Load a 16 bit literal to a register
   lit   #21,CG
   lit   #43,D

; Macro 'swap S,D'
; Swap low/high byte
   mov   S,CG
   mov   SWCG,D

; Macro 'pack S1,S2,D'
; Pack two low bytes to 16 bit word
   mov   S1,CG
   mov   S2,CGH
   mov   CG,D

; Works also with literals (not verry useful: use llit)
   lit   #21,CG
   lit   #43,CGH
   mov   CG,D

; Shift right 8 bits
   mov   S,CG
   mov   R8CG,D

; Shift left 8 bits
   mov   S,CG
   mov   L8CG,D

CG is also hardware address (HWA)

Code fragments hardware access
HWA   = CG           ; For more redability define HWA

   lit   #F8,HWA     ; Set hardware address to F8 (hex)
   mov   HWD,8#16    ; Move hardware data from F8 to register 16 (octal)

HWA is also used to point a program RAM address when P bit is set in the CTRL register.