MOV-1
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GHDL open-source VHDL simulator is used for designing the MOV-1 core:
http://ghdl.free.fr

GHDL builds an executable that can be run and outputs simulation data. With GTKWAVE this data can be viewed.

Xilinx ISE 10.1 + Spartan 3e starter kit is used for implementing the design. The Spartan 3e starter kit has a "sc3s500e-4fg320".

SMAL32 "Symbolic Macro Assembly Language 32bit" compiler is used to compile the assembly programs
http://homepage.cs.uiowa.edu/~jones/cross/smal32/

My copy of the site:
SMAL32

Table 1. The design is split up in five parts

mov1pkg.vhd

MOV-1 package

mov1cu.vhd

Control unit with program memory

mov1mu.vhd

Register file and data memory

mov1alu.vhd

Arithmetic Logic Unit

top.vhdl

mov1xxx.vhd wrap file

  • testbench.vhdl is uses when simulating

  • s3e_sk.ucf is used when implementing

Complexity

#|============= #|=============

Memory test (mov1mu.vhd)

Register R00 is preloaded with 7.

images/vhdl/registers/dmv.png
Figure 1. DMV: Decrement source register then move source to destination register.
images/vhdl/registers/mvd.png
Figure 2. MVD: Move source to destination register then decrement source register
images/vhdl/registers/mvi.png
Figure 3. MVI: Move source to destination register then increment source register